SystemVerilog – Advanced Verification for FPGA Design

Modern FPGA designs have tremendously advanced in both performance and capacity. Verification of this kind of designs has become a daunting task, especially the validation of the design against the specification and test plan.
SystemVerilog provides a comprehensive set of verification tools and is a natural extension to Verilog. It also provides constructs with clearer intent like enumerated types, integrated assertions and higher language constructs, which support design hierarchy and Object Oriented Programming (OOP). Powerful testbench features allow for more flexible and reusable testbench development, even in the context of a VHDL based design.
This workshop will give an overview about the SystemVerilog language and will introduce into new verification methodologies „Assertion Based Verification“, „Constrained Random Generation“ and „Functional Coverage“. The participant will learn how to use these powerful verification tools to speed up verification as well as to measure the verification progress and how these methodologies can be naturally applied to the verification of VHDL designs.

Target Group

  • FPGA design or verification engineers

Targets

  • Basic knowledge of SystemVerilog
  • Basics of OOP in SystemVerilog
  • Use of OOP for faster and more efficient, reusable testbench designs
  • Knowledge of the concept of an automated testbench
  • Introduction to assertions, constrained randomization and functional coverage

Applicable technologies

  • none

Requirements

  • Experience with VHDL or Verilog for Design and Verification

Dates


26.07.2021 | Berlin
Booking
11.10.2021 | Freiburg
Booking

Duration & Fee


Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material, beverages during breaks and lunch

Contact


Michael Schwarz

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