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RISC-V Architecture and FPGA Implementation

This course gives an introduction to the RISC-V architecture with an implementation in Xilinx FPGA technology. The implementation will be done on a Spartan-7 FPGA board and the related requirements will be explained.
The aim of the course is also to convey the definition of the Risc computer architecture and the instruction sets to the participants and to give an overview of the basic building blocks of the RISC-V hardware.
The principles of the RISC-V computer architecture, an optimized memory support for parallelized data and instruction accesses, are described.
An overview of the RISC-V instruction sets is also provided and the basic components of the RISC-V hardware are explained, as well as those of interrupt mechanisms. Relevant course content is also the arithmetic support of 32 bit/64 bit fixed point and floating point processing when using the RV32 or RV64 coreand its required data interfaces. Hardware aspects such as resource utilization, performance, pipelining, memory and bus architecture are discussed, and then in practice implemented and analyzed in the Vivado FPGA project.
In the following, the software toolchain is set up, which is to be used for the RISC-V CPU architecture in addition with Xilinx libraries in order to using also Xilinx IPs such as memory controllers or GPIOs. At the end of the course, simple applications will be created to achieve a successful test of the RISC-V system on the Xilinx Spartan-7 platform. The course conveys both theoretical and practical content.

Applicable technologies

  • XILINX 7 Series FPGAs


  • Basic knowledge of UDL programming
  • Comfort with the C/C++ programming language
  • Basic knowledge of XILINX FPGA design flow


21.06.2021 | Stuttgart
27.09.2021 | Frankfurt
01.12.2021 | Munich

Duration & Fee

Duration: 2 days

Fee: 1,500.00 €
net per person, including detailed training material, drinks in the breaks and lunch


Michael Schwarz

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