Webinar "Understanding Versal: the AI Engines" -register now-

Professional Vitis

To overcome bottlenecks due to sequential processing in embedded systems FPGAs provide massive parallelism and application fi tted data path. Xilinx supports such heterogenous FPGA and CPU designs with the Vitis Unifi ed Soft ware Platform. It allows projects for low level hardware drivers to be setup in one toolchain with the datapath projects that use high-level programming languages, e.g. OpenCL API for offl oading functionality from CPU to FPGA kernels. Th is program gets the soft ware developer started on the Vitis Unifi ed Soft ware Platform by introducing the Zynq SoC and MPSoC architectures. Soft ware development knowledge for the standalone platform is provided to cover the basic operation and low level services. Application development on the OS level is combined with insight into driver development. On this platform all is set for development, debug, and profi ling of C/C++ and RTL applications targeting data center (DC) and embedded (edge), e.g., on the Xilinx Alveo accelerator card or a Zynq Ultrascale Plut (ZCU104) board. Optimization topics and best practices will be provided all along.

The program teaches to:

  • Drive Vitis IDE and migrate from SDK to the Vitis Platform
  • Develop on the Standalone Software Platform
  • Customize board support packages (BSPs) for resource access based on the Xilinx Standalone library
  • Debug and integrate user applications
  • Employ best practices to enable educated design decisions
  • Build software applications with the OpenCLâ„¢ API to run hardware kernels on Alveo accelerator cards
  • Build applications using the OpenCL API and the Xilinx runtime (XRT) to schedule hardware kernels and control data flow
  • Understand Vitis platform execution model and XRT
  • Describe kernel development using C/C++ and RTL
  • Use the Vitis Analyzer tool to assess reports
  • Explain ways to optimize a design

Applicable technologies

  • Architecture: Xilinx Alveo accelerator cards, SoCs and ACAPs


  • Basic knowledge of Xilinx FPGA architecture
  • Comfort with the C/C++ programming language
  • Software development flow


12.06.2023 | Stuttgart

Duration & Fee

Duration: 5 days

Fee: 3,100.00 €
net per person including detailed training material, beverages during breaks and lunch


Michael Schwarz

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