Webinar "Secure Boot Features and Secure Boot Overview for Xilinx Versal ACAP" -register now-

Partially Constrained Record Types in VHDL-2008 or: How to wire components effectively? - WEBINAR

Since VHDL-2008, VHDL offers a technique to define record types for data busses like AXI4, mainly used by Xilinx, WishBone or Avalon that do not need to know how many bits will be used for address or data signals. This feature is called „partially constrained types“. Using this technique can speed up development time by reducing code lines, complexity and increasing readability as well as maintainability.

Registration:

Register for this webinar for free.

Date:

If the date does not suit you, you still have the possibility to watch this webinar. The webinar will be recorded and available "on demand" afterwards.

Live:

During the webinar you have time to ask questions directly to the trainer.

Material:

As a live participant you will receive a complete list of all answered questions during the webinar after the event.

Language:

The course language is English.


Requirements

  • none

Dates


Video on demand | Online
Booking

Duration & Fee


Duration: 1 hour

Fee: 0.00 €
PLC2 FREE WEBINAR

Contact


Michael Schwarz

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