The two-day workshop provides the system and algorithm developer with the XILINX Blockset Model Composer an introduction to a methodology to automatically generate higher-level FPGA hardware code.
Using Matlab Simulink with XILINX Model Composer enables the DSP module development where generated modules can easily be integrated in an overall FPGA project in different methods.
The user can choose exports like Matlab Simulink + Xilinx System Generator, XILINX Vivado HLS (High Level Synthesis) or Vivado HLx (Vhdl / Verilog).
With Xilinx Tool Model Composer, complex algorithms can be code-generated quiet quickly, without the skills of FPGA architectures or hardware programming languages.
Developers working on digital modeling, video processing, and algorithms use a higher method abstraction with this tool than with the Xilinx System Generator tool, highly efficient optimization results, and easy validation using Matlab Simulink.
The integration of own C/C++ templates is supported as well as manifold interfaces to FPGA modules like Xilinx HLS or VHDL/Verilog.
This workshop is recommended for participants working under Matlab Simulink on the target platforms of Xilinx technologies.
- XILINX FPGAS and ZYNQ families
- Basic knowledge in Digital Signal Processing
- Basic knowledge of ‘C’/’C++’
- Basic knowledge of Matlab/Simulink is an advantage
Duration & Fee
Duration: 2 days
net per person including detailed training material, beverages during breaks and lunch
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