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MicroBlaze Essentials and Workflow - LIVE ONLINE

This Online training describes the design architecture of the Xilinx MicroBlaze risc-processor and the workflow for the hardware- and software developer in a compact structure. Scalar processing in the FPGA or programmable logic is getting a wide variety as the processor core is highly configurable. Even multiple cores or redundant core implementation for safety requirements can be fulfilled. Standard bus interfaces (AXI) and proprietary interfaces (point-to-point) with the catalog of standard peripherals, memory solutions or inter processor communication (IPC) like this is useful for Zynq or Versal devices.

Attendees will get best understanding to build up simple or even advanced MicroBlaze system architectures and to drive the Vitis tools to develop application with the compilation and debugging tools.

The theoretical content is supplemented by exercises carried out by the participant.

Duration: 2 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Describe the various tools that encompass a Xilinx embedded design
  • Rapidly architect an embedded system containing the MicroBlaze™ processor
  • Create and integrate an IP-based processing system component
  • Develop software applications utilizing the Vitis unified platform tools
  • Use Xilinx debugger tools to troubleshoot user applications
  • Describes the boot methodology for the MicroBlaze system


  • Introduction
  • Embedded UltraFast Design Methodology
  • Overview of Embedded Hardware Development
  • MicroBlaze Processor Architecture
  • Driving the IP Integrator Tool
  • Interrupts Hardware Architecture and Support
  • AXI based Connectivity for Peripherals and Memory
  • Creating User Peripherals
  • Overview of Embedded Software Development
  • Driving the Vitis Tool
  • Baremetal Application Development and Debugging
  • Booting and MicroBlaze Bootloader

Applicable technologies

  • Xilinx FPGAs, Zynq SoC, Zynq UltraScale+ MPSoC and RFSoC, Versal


  • Basic knowledge in microprocessor architecture
  • Basic Knowledge of the Xilinx FPGA development
  • Comfort with the C/C++ programming language


19.12.2022 | Online

Duration & Fee

Duration: 2 days (4 hours each)

Fee: 1,000.00 €
net per person including detailed training material


Michael Schwarz