FPGA Design Techniques - LIVE ONLINE

For the successful implementation of digital circuits in the FPGA, the strong knowledge of the digital circuit’s basics is mandatory. The HDL based developing method simplifies the developing cycle, but for that, the developer must have the good knowledge of digital circuit design. Although most of the developers basically know the digital components like combinational and sequential and their usage, it is very important to know the FPGA architecture for which a digital design should be implemented.
After the review of combinational and sequential circuits, the design of combinatorial circuits, sequential circuits and sequential systems will be discussed.
In almost every digital design there is Clock Domain Crossing where CDC Analysis and synchronization circuits are needed, which is described. Finally, Timing Constraints and Timing Analysis is discussed.

The theoretical content is supplemented by exercises carried out by the participant.
 

Duration: 3 mornings of 4 hours each

Times:    9.00 a.m. - 11.00 a.m.    Lecture part 1

              11.00 a.m. - 11.15 a.m.  15 minute break

              11.15 a.m. - 1.15 p.m.    Lecture part 2

Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.

After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of 
requirements to be done in advanced.

Course Objectives:

  • Describe the internal structures of FPGAs
  • Describe the clocking structures of FPGAs
  • Understand synchronous design techniques
  • Understand Clock Domain Crossing
  • Describe synchronization Circuits
  • Understand Timing Constraints and Timing Analysis

Agenda:

Introduction to the FPGA Architecture (Xilinx 7-Series)

  • Combinatorial Resources
  • Sequential Resources
  • Embedded Resources
  • Clock Resources
  • RAMs and FIFOs
  • Input / Output Resources

Design Techniques

  • Synchronous vs. Asynchronous
  •  Synchronous Design Technique
  • Designing with RAMs and FIFOs
  • Designing with State Machines
  • Designing Interfaces
  • Rules and Best Practice

Clock Domain Crossing (CDC)

  • Sampling and Capturing Data in Multiple Clock Domains
  • Synchronization Circuits
  • CDC Analysis

Timing Optimization

  • Timing Specification
  • Timing Constraints
  • Timing Analysis

Labs:

  • Using MMCMs
  • Using RAMs and FIFOs
  • Design of an UART
  • Low Speed DAC Interface using SPI
  • Low Speed ADC Interface using SPI
  • High Speed ADC Interfaces using LVDS

Applicable technologies

  • All kind of FPGA technologies

Requirements

  • none

Dates


15.06.2021 | Online
Booking

Duration & Fee


Duration: 3 days (4 hours each)

Fee: 1,500.00 €
net per person including detailed training material

Contact


Michael Schwarz