Expert Versal AI Engine
With the Versal Adaptive Compute Acceleration Platform (ACAP) family XILINX introduces versions of these FPGA with a special feature, the AI Engine. The AI Engine offers high performance, low latency capabilities for advanced data processing.
This course shows the application acceleration with C/C++ kernels on Versal AI Engine. From start the elements of the Versal AI Engine are described, the VLIW processing unit, the connectivitiy through the available interfaces and the memory hierarchy in the regular grid of these AIE tiles. With the Vitis tools the AI Engine is set up to run acceleration functions written in C/C++ code. We will show how to implement discrete AI kernels with the full set of intrinsic functions with XChessDE or the Vitis tool-chain. Upon understanding basic kernel programming a tool flow is presented that uses dataflow graphs to connect multiple kernels. Deploying these dataflow graphs this course also shows the system level design flow with AI Engine based kernels in Vitis. The data movement between compute domains, i.e. within the AI Engine and towards NoC and PL is presented and the different interface types and connection capabilities are explained. This course teaches how to analyze and optimize designs with the tooling in the Vitis platform. To deploy such heterogeneous systems, the data flow graph may route multiple compute domains as PL and AI Engine. The advanced features to interface these graph elements effectively, such as streams, cascade stream, buffer location constraints, run-time parameterization and respective APIs are explained and can be experienced in hands on lab exercises. It will be shown how such data processing graphs can be added into a Versal device system design.
- XILINX Versal AI Core Series
- Basic knowledge of embedded controller
- Basic knowledge of Vitis Toolflow
- Basic knowledge of ‘C’/’C++’
Duration & Fee
Duration: 5 days
net per person, including detailed training material, drinks in the breaks and lunch
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