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Dynamic Function eXchange DFX

This course demonstrates how to use the Vivado® Design Suite to construct, implement, and download a Partially Reconfigurable (PR) FPGA design.
You will gain a firm understanding of PR technology and learn how successful PR designs are completed. You will also identify best design practices and understand the subtleties of the PR design flow.
This course covers both the tool flow and mechanics of successfully creating a PR design. It also describes several techniques focusing on appropriate coding styles for a PR system as well as system-level design considerations and practical applications.
The PR design approach allows strategies for non-realtime multiplexing hardware functions by exchanging partial bitstream configuration files. This is an advanced methodology for in-system-programming FPGA devices.


Applicable technologies

  • XILINX FPGAs, SoC, MPSoC & RFSoC

Requirements

  • Basic knowledge of FPGA technology
  • Basic knowledge in VHDL or Verilog
  • Basic knowledge of the Vivado design flow
  • recommended: knowledge of microprocessors

Dates


17.10.2022 | Freiburg
Booking

Duration & Fee


Duration: 2 days

Fee: 1,500.00 €
net per person including detailed training material, beverages during breaks and lunch

Contact


Michael Schwarz

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