Webinar "Xilinx Versal ACAP - Creating a Custom Embedded Platform" -register now-

Designing with PCI Express

With the availability of the recent FPGA families, the PCI Express (PCIe) IP cores allow for very effective solutions- in particular when using the embedded IP block.
At the beginning of this class, an introduction to the vocabulary and the transmission protocol is given along with details on the structure and content of data packets. This is a solid foundation for building your own application. After that, the main aspects of this training class are simulation and implementation of a provided example design.
This way, the learning experience is the most realistic while allowing to easily put the theory into reality. The interface between the core block and the user application is especially emphasized. The available signals and their correct usage are discussed in the necessary detail.
During the training, the target technology will be a Kintex-7 / Kintex UltraScale based XILINX evaluation board. The working principles and the protocol information however, are equally valid for other technologies, too.


Applicable technologies

  • XILINX 7 Series FPGAs
  • all UltraScale Architectures
  • Versal ACAP

Requirements

  • Basic knowledge of VHDL
  • Knowledge of Xilinx design tool flows
  • Basic knowledge of FPGA technology

Dates


06.09.2021 | Munich
Booking
06.12.2021 | Berlin
Booking

Duration & Fee


Duration: 3 days

Fee: 2,100.00 €
netto per participant incl. documents

Contact


Michael Schwarz

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