Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Learn how to implement a Xilinx PCI Express® core in custom applications to improve time to market with the PCIe® core design.
The focus is on:
- Constructing a Xilinx PCI Express system within the customer education reference design
- Enumerating various Xilinx PCI Express core products
- Identifying the advanced capabilities of the PCIe specification
This course also focuses on the AXI Streaming interconnect.
The theoretical content is supplemented by exercises carried out by the participant.
Duration: 4 mornings of 4 hours each
Times: 9.00 a.m. - 11.00 a.m. Lecture part 1
11.00 a.m. - 11.15 a.m. 15 minute break
11.15 a.m. - 1.15 p.m. Lecture part 2
Exercises: self paced by the participants. Estimated time for completion appr. 2-3 hours. At the end of a lecture, the exercises to be performed by participants are discussed. The results / sample solutions are presented by the trainer the next day.
After registration: the participant receives the presentation documents in electronic form (PDF) as well as the workbook for the exercises, the login data and a list of
requirements to be done in advanced.
After completing this comprehensive training, you will have the necessary skills to:
- Selecting the appropriate core for your application
- Specifying requirements of an endpoint application
- Connecting this endpoint with the core
- Utilizing FPGA resources to support the core
- Constructing a basic PCIe system
- Simulating the design
- Implement the design
- Debug the design
- Xilinx PCI Express Solutions
- Connecting Logic to the Core
- PCIe Core Customization
- Packet Formatting Details
- Simulating a PCIe System Design
- Endpoint Application Considerations
- PCI Express in Embedded Systems
- Application Focus DMA
- Design Implementation and PCIe Configuration
- Root Port Applications
- Debugging and Compliance
- Interrupts and Error Management
Lab 1: Constructing the PCIe Core – This lab familiarizes you with the necessary flow for generating a Xilinx Integrated PCI Express Endpoint core from the IP catalog. You will select appropriate parameters and create the PCIe core used throughout the labs.
Lab 2: Simulating the PCIe Core – This lab demonstrates the timing and behavior of a typical link negotiation using the Vivado simulator. You will observe and capture transaction layer packets.
Lab 3: Using the PCI Express Core in IP Integrator – This lab familiarizes you with all the necessary steps and recommended settings to use the PCIe solutions in an IP integrator block design.
Lab 4: Exploring the Xilinx DMA – This lab familiarizes you with all the necessary steps to set up and perform DMA transfers.
Lab 5: Implementing the PCIe Design – This lab familiarizes you with all the necessary steps and recommended settings to turn the HDL source to a bitstream by using the Tandem configuration mode.
Lab 6: Debugging the PCIe Design – This lab illustrates how to use the Vivado logic analyzer to monitor the behavior of the core and a small endpoint application for proper operation.
Note: Lab 5 and Lab 6 require a running PCIe system using the KCU105 board. These labs will run remotely. All other labs can run locally.
- UltraScale architectures
- Experience with PCIe specification protocol
- Basic knowledge in VHDL or Verilog
- Some experience with Xilinx implementation tools
- Some experience with a simulation tool, preferably the Vivado® simulator
- Moderate digital design experience