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DDR4 Interfacing with XILINX FPGAs

The new XILINX UltraScale architectures allow very fast interfaces to external memories based on new and improved structures on silicon and a new memory wizard as well.
Realization challenges are shifting from chip level to board level with the new UltraScale architectures. The very high data rates required extreme accuracy in PCB design.
The 3-day workshop “DDR4 Interfacing with XILINX FPGAs” targets to hardware designers, as well as to System Architects and Layout designers, who want to implement DDR4 interfaces in a system successfully.
This workshop starts with a comparison between DDR3 and DDR4 memories. The DDR4 enhancements are discussed together with the new features and operational details of DDR4 memories.
All design steps are described: DDR4 design generation, functional simulation, and implementation. The design will be tested on real hardware. Special focus is on physical layer – signal integrity. Parameters for signal quality and timing are covered.
Practical design and verification examples are discussed. Simulation options on PCB level are described and demonstrated during labs. The participants will learn how to derive design rules for PCB design. Methodical tips and tricks complete the content.


Applicable technologies

  • All UltraScale FPGA/MPSoC architectures
  • Versal ACAP

Requirements

  • Comfort with the VHDL programming language

Dates


01.12.2020 | Stuttgart
Booking
08.02.2021 | Berlin
Booking
19.07.2021 | Frankfurt
Booking
01.12.2021 | Stuttgart
Booking

Duration & Fee


Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material, beverages during breaks and lunch

Contact


Michael Schwarz

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