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Compact ZYNQ UltraScale+ MPSoC for HW Designers

This three-day course provides both the tool- and architecture-specific aspects necessary for development with the XILINX ZYNQ UltraScale+ MPSoC device.
At the beginning, special attention will be paid to the Embedded Design Flow.
The course focuses on embedded hardware development with the XILINX VIVADO tool using the IP-Integrator, which also covers software development with the XILINX SDK.
Then the overall architecture of the ZYNQ UltraScale+ MPSoC Processing System (PS) is discussed.
For the connection of AXI-based IPs in the Programmable Logic (PL) to the Processing System (PS) it is essential to understand the AXI protocol as well as the Interrupt structures.
The final section of this course consists of creating and verifying custom IP cores with an AXI based interface port to the Processing System.


Applicable technologies

  • XILINX ZYNQ UltraScale+ MPSoC & RFSoC

Requirements

  • Basic knowledge of digital system architectures
  • Basic Knowledge of VHDL or Verilog language
  • Basic knowledge of C / C ++ is an advantage

Dates


24.08.2021 | Berlin
Booking
08.11.2021 | Munich
Booking

Duration & Fee


Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material, beverages during breaks and lunch

Contact


Michael Schwarz