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Compact VHDL for Synthesis

Programmable logic devices like FPGAs have been established in the daily life. They can be found in mobile phones, IoT devices, cars or cloud data centers. Their area of operation is as broad as their size. FPGAs are used as, but not limited to: protocol adapters, signal converters, or accelerators for video, radar and sensor data processing.
The design of digital circuits in this scale needs a powerful hardware description language which offers different levels of abstraction, so an engineer can create a digital hardware design in a quick and effective way. VHDL fulfills these requirements.
VHDL is a strongly typed hardware description language which prohibits typical programming mistakes in the coding phase. Usually, VHDL is used on the register transfer level (RTL) to design digital circuits of any complexity. Apart from the language constructs for synthesis, VHDL offers a wide range of functionality to describe complex verification models. Thus, it is possible verify digital designs from simple gate up to complicated System-on-Chip (SoC) before going to lab tests.
This workshop will teach the synthesis relevant aspects of the VHDL hardware description language based on the IEEE Std. 1076-2008 language revision. The theoretical knowledge will be deepened with selected examples and labs on PC.
A basic knowledge in digital circuit design (gates, multiplexers, flip-flops, memories), as well as the understanding of basic principles of scripting or programming languages are welcome.

Applicable technologies

  • All (FPGA technology independent)


  • basic knowledge in digital circuit design (e.g. Compact FPGA Design Techniques)


19.06.2023 | Frankfurt

Duration & Fee

Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material, beverages during breaks and lunch


Michael Schwarz

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