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Compact Versal ACAP for SW Designers

This 3-day course will enable the software developer to get the best possible start on software development for the Versal ACAP family. This first explains the Versal ACAP architecture and the unified Vitis Software Development tool with toolchain and methods for the embedded design using the processors and toolchains for hardware acceleration using DSP engines, AI engines or adaptable engines in the programmable logic. Symmetric and asymmetric OS support, Open-source Linux builds using Yocto and/or PetaLinux, FreeRTOS usage for the real-time processing unit, Hypervisor support and at least mechanisms of boot configurations are shown and elaborated with lab exercises.
Debugging in simulation, emulation and hardware debugging - various methods are integral part of the Vitis tool. While multiple processors in the Versal architecture are often not running simultaneously in full performance mode, the power management of resources is software programmable and so enables power reduction in the runtime system. The management of boot images and boot loaders is also covered in the course.

Applicable technologies

  • XILINX Versal ACAP


  • Basic knowledge of processor architectures
  • Comfort with the C/C++ programming language
  • Basic knowledge of Xilinx FPGA architecture


on request

Duration & Fee

Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material, beverages during breaks and lunch


Michael Schwarz