Webinar "Xilinx Versal ACAP - From FPGA to Platform" -register now-

Compact Versal ACAP for HW Designers

With the new XILINX ACAP family (Adaptive Compute Acceleration Platform) hardware developers are enabled for the classic methods of HDL development, i.e. also by using HLS tool. And with Vitis a huge capability of methods and libraries for hardware acceleration in the context of processor-based applications is given for the software and embedded developers. This course conveys both the tool-specific and the architecture-specific aspects that are necessary and relevant for hardware development, which not only concerns the PL, but also using in a good way existing Versal Chip resources that can be used for hardware functions and IPs. These are memory controllers, DMAs, DSP engines, AI engines, peripheral interface management and I/O interfaces. Good team-based design by hardware and software developers is important, to enable a productive way of system integration with the Vivado and Vitis tool.
This is also important insofar when abstract s/w methods do not meet the requirement so that the hardware developer get a solution on a lower abstraction level of programming. Floating point operations also play an increasingly important role, which is also enabled with Versal ACAP DSP Engines now.
Connectivity management is usually in the hands of the hardware developer. Here it is important to use interfaces based on AXI technology to manage the throughput rates, latencies under synchronization rules and also its initialization usually at boot time. With ACAP, NoC (Network-on-Chip) was introduced so that this bus management can also be changed and optimized at run-time level to achieve the right balance for the data traffic of multiple parallel engines, IPs and their memory accesses. Finally, the topics of power-, thermal-estimation and PCB design rules are the topics in this course.

Applicable technologies

  • XILINX Versal ACAP


  • Basic knowledge of Xilinx FPGA architecture
  • Basic knowledge of digital system architectures
  • Basic knowledge of VHDL
  • Comfort with the XILINX Vivado Flows


28.04.2021 | Frankfurt
19.07.2021 | Munich
20.10.2021 | Stuttgart

Duration & Fee

Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material, beverages during breaks and lunch


Michael Schwarz