Webinar "On the development of FPGAs according to DO254" -register now-


One thing coming increasingly to the fore is the acceleration of computation intensive applications such as used in e.g. image processing or specific DSP algorithms. Vivado High Level Synthesis (HLS) allows to quickly and efficiently port those algorithms to hardware. Usage of ‘C’ based high level languages like ‘C’, ‘C++’ or ‘SystemC’ automates the implementation and optimisation of FPGA designs by converting the ‘C’ based code to HDL (VHDL or Verilog).
This allows various scenarios when used in combination with ZYNQ-7000 SoC technology: For Example ‘C++’ algorithms can be run either on the ZYNQ as software or they can be implemented in the programmable logic as hardware. Moreover, targeting hardware, the algorithms can be optimised for speed, latency or resource usage. The focus of this workshop is put on using the HLS environment to create hardware accelerators for computation intensive applications. Working on exercises, the attendee creates ‘C’/’C++’ programs that are run as software on a MicroBlaze/ ZYNQ processor in a first step. In a second step, the code is converted to RTL code and gets implemented.
This workshop’s target audience are attendees with a first experience using Vivado HLS as well as basic knowledge of ‘C’/’C++’ and VHDL. Furthermore, the attendee should be familiar with the ZYNQ device or the Micro-Blaze processor and the associated development tools.

Applicable technologies

  • XILINX 7 Series FPGAs
  • UltraScale FPGAs


  • Experience in Using ZYNQ-SoC and/or MicroBlaze of advantage
  • Basic knowledge of ‘C’/’C++’
  • Basic knowledge of Vivado HLS


on request

Duration & Fee

Duration: 3 days

Fee: 2,100.00 €
net per person including detailed training material, beverages during breaks and lunch


Michael Schwarz

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