Webinar "Xilinx Versal ACAP - From FPGA to Platform" -register now-

Our training courses - Knowledge imparted competently

Each of our training courses has a clear goal: To impart knowledge competently. We carry out this goal, on the one hand, with a wide range of offerings, and on the other hand, with very customized support during the training courses.

Our E-Team experts follow a learning guide, they always focus on the individual strengths and needs of the participants. They focus on technical content and refrain from marketing aspects. Very important for us is: The knowledge we provide is always up to date with the respective technology. We train you in various areas involving embedded systems (among others): Easy Start, FPGA, DSP, Languages, Connectivity, Embedded, Verification, Image Processing, Technology.

Our experts will be at your side in more than 80 highly customised and specifically designed training courses. Every year, we teach more than 1,100 engineers, technicians, managing directors, buyers, project managers, developers and administrative staff at various locations in Germany or in-house. Our customers include hundreds of companies – mainly from Germany, Switzerland and Eastern Europe. We offer participants from the automotive, electronics, aerospace, military, medical, communication or IoT sectors a wide range of training in Xilinx technologies and hardware description languages. Besides our Face-to-Face trainings PLC2 offers also online trainings. Webinars, Shorties and PLC2 online trainings.

The length of the training is based on the trained content: You or your staff can attend a free one-day seminar, a two- /three-day workshop, or a five-day power workshop. Customer-specific training can also run over a period of several months. The PLC2 long-term training is an additional chance to get further education.

Easy Start

Date
Title
Location
11.02.2021
Easy Start Embedded for ZYNQ-7000 SoC Systems
Freiburg
22.02.2021
Easy Start FPGA Vivado - LIVE ONLINE
Online
01.03.2021
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Stuttgart
09.03.2021
Easy Start FPGA Vivado
Berlin
10.05.2021
Easy Start Embedded for ZYNQ-7000 SoC Systems
Frankfurt
17.05.2021
Easy Start FPGA Vivado
Munich
01.07.2021
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Frankfurt
22.07.2021
Easy Start Embedded for ZYNQ-7000 SoC Systems
Munich
05.08.2021
Easy Start FPGA Vivado
Stuttgart
04.10.2021
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Berlin
18.10.2021
Easy Start Embedded for ZYNQ-7000 SoC Systems
Stuttgart
22.11.2021
Easy Start FPGA Vivado
Frankfurt
01.12.2021
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Freiburg
Upon request
Easy Start Embedded PetaLinux

FPGA

Date
Title
Location
01.02.2021
Professional VHDL
Freiburg
02.02.2021
Vivado IP Flow - LIVE ONLINE
Online
03.02.2021
Compact Verilog
Munich
08.02.2021
Professional FPGA
Stuttgart
08.02.2021
Git for EDA Tool Flows - LIVE ONLINE
Online
15.02.2021
Stuttgart
16.02.2021
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
16.02.2021
VHDL for Simulation - LIVE ONLINE
Online
16.02.2021
VIVADO Design Suite Tool Flow
Freiburg
17.02.2021
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Freiburg
22.02.2021
Professional FPGA Design Techniques
Freiburg
22.02.2021
VHDL for Synthesis - LIVE ONLINE
Online
22.02.2021
Professional VHDL Testbenches and Verification with OSVVM
Frankfurt
22.02.2021
SystemVerilog – Advanced Verification for FPGA Design
Frankfurt
24.02.2021
Vivado Logic Analyzer - LIVE ONLINE
Online
25.02.2021
UVM Made Easy for FPGA Designers
Frankfurt
02.03.2021
FPGA Designer - long term training
Freiburg
04.03.2021
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
08.03.2021
Vivado Design Flow - LIVE ONLINE
Online
08.03.2021
Developing for Mission Critical FPGA & SoC
Munich
09.03.2021
Introduction to Verification with OSVVM - LIVE ONLINE
Online
11.03.2021
Debugging Techniques Using the VIVADO Logic Analyzer
Berlin
15.03.2021
Compact UltraScale/UltraScale+
Munich
15.03.2021
Stuttgart
22.03.2021
Professional VIVADO
Freiburg
22.03.2021
Compact VHDL for Synthesis
Freiburg
23.03.2021
Advanced Verification with OSVVM - LIVE ONLINE
Online
24.03.2021
Designing with the Spartan-7 Family
Freiburg
25.03.2021
Compact VHDL for Simulation
Freiburg
29.03.2021
Compact VHDL Testbenches and Verification with OSVVM
Stuttgart
08.04.2021
Dynamic Function eXchange or Partial Reconfiguration
Frankfurt
19.04.2021
SystemVerilog – Advanced Verification for FPGA Design
Munich
19.04.2021
Professional VHDL
Munich
22.04.2021
UVM Made Easy for FPGA Designers
Munich
26.04.2021
Professional FPGA Design Techniques
Freiburg
03.05.2021
Compact FPGA Design Techniques
Frankfurt
10.05.2021
Compact VHDL Testbenches and Verification with OSVVM
Freiburg
17.05.2021
Professional FPGA
Frankfurt
17.05.2021
Freiburg
26.05.2021
Compact Verilog
Freiburg
07.06.2021
Professional VHDL Testbenches and Verification with OSVVM
Freiburg
07.06.2021
VIVADO Design Suite Tool Flow
Stuttgart
08.06.2021
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Stuttgart
14.06.2021
Debugging Techniques Using the VIVADO Logic Analyzer
Freiburg
16.06.2021
Compact UltraScale/UltraScale+
Freiburg
21.06.2021
Designing with the Spartan-7 Family
Frankfurt
21.06.2021
Compact VHDL for Synthesis
Frankfurt
21.06.2021
Developing for Mission Critical FPGA & SoC
Berlin
24.06.2021
Compact VHDL for Simulation
Frankfurt
12.07.2021
Dynamic Function eXchange or Partial Reconfiguration
Stuttgart
12.07.2021
Professional FPGA Design Techniques
Freiburg
19.07.2021
Professional VIVADO
Freiburg
19.07.2021
Professional FPGA
Freiburg
19.07.2021
Frankfurt
26.07.2021
Professional VHDL
Freiburg
26.07.2021
SystemVerilog – Advanced Verification for FPGA Design
Berlin
29.07.2021
UVM Made Easy for FPGA Designers
Berlin
02.08.2021
Compact FPGA Design Techniques
Stuttgart
16.08.2021
Compact VHDL Testbenches and Verification with OSVVM
Berlin
08.09.2021
Compact Verilog
Frankfurt
13.09.2021
Compact VHDL for Synthesis
Stuttgart
14.09.2021
FPGA Designer - long term training
Freiburg
16.09.2021
Debugging Techniques Using the VIVADO Logic Analyzer
Stuttgart
16.09.2021
Compact VHDL for Simulation
Stuttgart
20.09.2021
Professional VHDL Testbenches and Verification with OSVVM
Freiburg
20.09.2021
Developing for Mission Critical FPGA & SoC
Freiburg
20.09.2021
VIVADO Design Suite Tool Flow
Frankfurt
21.09.2021
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Frankfurt
29.09.2021
Designing with the Spartan-7 Family
Berlin
29.09.2021
Compact UltraScale/UltraScale+
Frankfurt
04.10.2021
Professional VIVADO
Freiburg
04.10.2021
Compact VHDL Testbenches and Verification with OSVVM
Munich
11.10.2021
Professional FPGA
Munich
11.10.2021
SystemVerilog – Advanced Verification for FPGA Design
Freiburg
11.10.2021
Berlin
14.10.2021
UVM Made Easy for FPGA Designers
Freiburg
18.10.2021
Professional VHDL
Frankfurt
25.10.2021
Dynamic Function eXchange or Partial Reconfiguration
Freiburg
25.10.2021
Compact FPGA Design Techniques
Berlin
08.11.2021
Professional VHDL Testbenches and Verification with OSVVM
Stuttgart
08.11.2021
VIVADO Design Suite Tool Flow
Berlin
09.11.2021
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Berlin
11.11.2021
Designing with the Spartan-7 Family
Stuttgart
15.11.2021
Professional FPGA Design Techniques
Freiburg
17.11.2021
Compact UltraScale/UltraScale+
Stuttgart
22.11.2021
Compact VHDL for Synthesis
Munich
25.11.2021
Compact VHDL for Simulation
Munich
01.12.2021
Compact Verilog
Stuttgart
01.12.2021
Freiburg
01.12.2021
Debugging Techniques Using the VIVADO Logic Analyzer
Frankfurt
06.12.2021
Professional VIVADO
Freiburg
06.12.2021
Developing for Mission Critical FPGA & SoC
Frankfurt
13.12.2021
Professional VHDL
Freiburg
Upon request
Upon request
FPGA Power Optimization
Upon request
Advanced Vivado-Tcl-Scripting
Upon request
Designing with the XILINX Analog Mixed Signal Solution
Upon request
First-time Right Methods in ASIC and FPGA Design - WEBINAR
Online
Video on demand
Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE
Recorded
Video on demand
New Features in VHDL 2019 - WEBINAR
Online

Embedded

Date
Title
Location
29.01.2021
Xilinx Versal ACAP - From FPGA to Platform - WEBINAR
Online
01.02.2021
Compact Versal ACAP for SW Designers
Stuttgart
03.02.2021
Acceleration Kernels with Versal AI Engine - WEBINAR
Online
08.02.2021
Compact Vitis for Software Designers
Freiburg
08.02.2021
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Frankfurt
10.02.2021
ZYNQ-7000 SoC System Architecture
Frankfurt
11.02.2021
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
16.02.2021
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
17.02.2021
Compact Vitis for Acceleration
Munich
22.02.2021
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Stuttgart
22.02.2021
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Online
22.02.2021
Designing with RF Data Converters
Berlin
25.02.2021
Developing Multimedia Solutions with the VCU and GStreamer
Stuttgart
02.03.2021
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Online
03.03.2021
Stuttgart
08.03.2021
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
08.03.2021
Professional ZYNQ UltraScale+ MPSoC
Freiburg
08.03.2021
Frankfurt
08.03.2021
PCI Express Hands-on System Development
Freiburg
10.03.2021
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Online
11.03.2021
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
Online
15.03.2021
Professional Versal ACAP
Munich
15.03.2021
Compact Python for Embedded
Stuttgart
15.03.2021
Professional Python for Embedded
Stuttgart
15.03.2021
Compact ZYNQ-7000 SoC for HW Designers
Stuttgart
15.03.2021
ZYNQ UltraScale+ MPSoC System Architecture
Stuttgart
15.03.2021
RISC-V Architecture and FPGA Implementation
Freiburg
15.03.2021
Embedded Design with PetaLinux Tools
Stuttgart
17.03.2021
Compact ZYNQ-7000 SoC for SW Designers
Munich
22.03.2021
AXI Interface Technology
Freiburg
22.03.2021
Frankfurt
29.03.2021
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Munich
29.03.2021
RISC-V Core Verification and Compliance Testing
Frankfurt
07.04.2021
FPGA Embedded Designer - long term training
Freiburg
12.04.2021
Freiburg
12.04.2021
Professional ZYNQ-7000 SoC
Freiburg
12.04.2021
Developing Multimedia Solutions with the VCU and GStreamer
Freiburg
26.04.2021
Versal ACAP System Architecture
Frankfurt
28.04.2021
Compact Versal ACAP for HW Designers
Frankfurt
03.05.2021
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Frankfurt
03.05.2021
Designing with RF Data Converters
Freiburg
04.05.2021
Compact Vitis for Acceleration
Berlin
17.05.2021
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Freiburg
17.05.2021
Compact Vitis for Software Designers
Frankfurt
26.05.2021
Compact Versal ACAP for SW Designers
Frankfurt
01.06.2021
ZYNQ-7000 SoC System Architecture
Berlin
01.06.2021
RISC-V Core Verification and Compliance Testing
Munich
07.06.2021
Professional ZYNQ UltraScale+ MPSoC
Frankfurt
07.06.2021
Freiburg
08.06.2021
PCI Express Hands-on System Development
Berlin
14.06.2021
Professional Versal ACAP
Stuttgart
14.06.2021
Compact Python for Embedded
Freiburg
14.06.2021
Professional Python for Embedded
Freiburg
14.06.2021
Compact ZYNQ-7000 SoC for HW Designers
Freiburg
14.06.2021
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Berlin
14.06.2021
Compact ZYNQ-7000 SoC for SW Designers
Berlin
21.06.2021
ZYNQ UltraScale+ MPSoC System Architecture
Frankfurt
21.06.2021
RISC-V Architecture and FPGA Implementation
Stuttgart
21.06.2021
Stuttgart
23.06.2021
Embedded Design with PetaLinux Tools
Frankfurt
28.06.2021
Frankfurt
28.06.2021
AXI Interface Technology
Frankfurt
12.07.2021
Munich
14.07.2021
Developing Multimedia Solutions with the VCU and GStreamer
Frankfurt
19.07.2021
Compact Versal ACAP for HW Designers
Munich
26.07.2021
Professional ZYNQ-7000 SoC
Freiburg
02.08.2021
Freiburg
10.08.2021
Compact Versal ACAP for SW Designers
Freiburg
10.08.2021
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Berlin
16.08.2021
Compact Vitis for Acceleration
Freiburg
24.08.2021
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Berlin
30.08.2021
Versal ACAP System Architecture
Stuttgart
01.09.2021
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Frankfurt
01.09.2021
Compact Vitis for Software Designers
Berlin
06.09.2021
Compact Python for Embedded
Frankfurt
06.09.2021
Professional Python for Embedded
Frankfurt
06.09.2021
Freiburg
06.09.2021
RISC-V Core Verification and Compliance Testing
Berlin
09.09.2021
ZYNQ-7000 SoC System Architecture
Freiburg
13.09.2021
Professional ZYNQ UltraScale+ MPSoC
Freiburg
13.09.2021
Stuttgart
20.09.2021
Professional Versal ACAP
Frankfurt
20.09.2021
Designing with RF Data Converters
Stuttgart
20.09.2021
PCI Express Hands-on System Development
Frankfurt
22.09.2021
Compact ZYNQ-7000 SoC for SW Designers
Freiburg
27.09.2021
Compact ZYNQ-7000 SoC for HW Designers
Frankfurt
27.09.2021
ZYNQ UltraScale+ MPSoC System Architecture
Freiburg
27.09.2021
RISC-V Architecture and FPGA Implementation
Frankfurt
27.09.2021
Embedded Design with PetaLinux Tools
Berlin
27.09.2021
AXI Interface Technology
Berlin
04.10.2021
Developing Multimedia Solutions with the VCU and GStreamer
Berlin
04.10.2021
FPGA Embedded Designer - long term training
Freiburg
06.10.2021
Compact Versal ACAP for SW Designers
Berlin
18.10.2021
Professional ZYNQ-7000 SoC
Freiburg
20.10.2021
Compact Versal ACAP for HW Designers
Stuttgart
25.10.2021
Frankfurt
02.11.2021
Compact Vitis for Acceleration
Frankfurt
03.11.2021
Compact ZYNQ-7000 SoC for SW Designers
Frankfurt
08.11.2021
Professional Python for Embedded
Berlin
08.11.2021
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Munich
08.11.2021
Compact Python for Embedded
Berlin
09.11.2021
Versal ACAP System Architecture
Munich
11.11.2021
ZYNQ-7000 SoC System Architecture
Munich
15.11.2021
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Freiburg
15.11.2021
Berlin
22.11.2021
Professional Versal ACAP
Freiburg
29.11.2021
AXI Interface Technology
Munich
29.11.2021
Embedded Design with PetaLinux Tools
Munich
01.12.2021
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Stuttgart
01.12.2021
RISC-V Architecture and FPGA Implementation
Munich
06.12.2021
ZYNQ UltraScale+ MPSoC System Architecture
Munich
06.12.2021
Compact ZYNQ-7000 SoC for HW Designers
Munich
06.12.2021
PCI Express Hands-on System Development
Stuttgart
08.12.2021
Compact Vitis for Software Designers
Munich
13.12.2021
RISC-V Core Verification and Compliance Testing
Stuttgart
13.12.2021
Professional ZYNQ UltraScale+ MPSoC
Frankfurt
13.12.2021
Designing with RF Data Converters
Munich
13.12.2021
Berlin
20.12.2021
Munich
Upon request
Debug your Linux – Praktisches Debuggen auf echter Hardware
Upon request
Upon request
High-Speed Ethernet – Hands-On System Development
Upon request
Professional MicroBlaze System Design
Upon request
Migrate to Real-Time OS: Hands-On System Development
Upon request
Embedded Linux Development with Yocto Project
Upon request
Embedded Linux Driver Development
Upon request
Real-Time Control System Development using RTOS
Upon request
Essentials of Microprocessors
Video on demand
Running Multiple OS using XEN Hypervisior for Zynq US+ MPSoC - WEBINAR
Online
Video on demand
Dynamic Function eXchange (DFX) – reloading partial h/w function using Zynq MPSoC - WEBINAR
Online

DSP & Image Processing

Date
Title
Location
01.02.2021
DSP Design using System Generator
Munich
01.02.2021
Expert DSP Design using System Generator
Munich
04.02.2021
Model Composer
Munich
16.02.2021
Frankfurt
01.03.2021
Vivado High-Level-Synthese for Hardware Designers - LIVE ONLINE
Online
19.04.2021
DSP Design using System Generator
Frankfurt
19.04.2021
Expert DSP Design using System Generator
Frankfurt
22.04.2021
Model Composer
Frankfurt
10.05.2021
Freiburg
02.08.2021
Stuttgart
06.09.2021
DSP Design using System Generator
Freiburg
06.09.2021
Expert DSP Design using System Generator
Freiburg
09.09.2021
Model Composer
Freiburg
22.11.2021
Munich
06.12.2021
Expert DSP Design using System Generator
Berlin
06.12.2021
DSP Design using System Generator
Berlin
09.12.2021
Model Composer
Berlin

Connectivity

Date
Title
Location
02.02.2021
ZYNQ – Board Design and High Speed Interfacing
Frankfurt
16.02.2021
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Online
17.02.2021
Designing with PCI Express
Stuttgart
25.02.2021
PCIe Protocol Overview - LIVE ONLINE
Online
02.03.2021
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Online
08.03.2021
UltraScale FPGAs – Connectivity
Munich
15.03.2021
High-Speed Memory Interfacing
Berlin
22.03.2021
VERSAL ACAP Connectivity (3 days)
Frankfurt
22.03.2021
VERSAL ACAP Connectivity (5 days)
Frankfurt
19.04.2021
Professional PCI Express
Berlin
10.05.2021
Designing with Multi-Gigabit Serial I/O
Berlin
17.05.2021
Designing with PCI Express
Freiburg
20.05.2021
Designing with Ethernet MAC Controllers
Stuttgart
26.05.2021
ZYNQ – Board Design and High Speed Interfacing
Munich
07.06.2021
Signal Integrity
Berlin
10.06.2021
FPGA Board-Design
Berlin
14.06.2021
High-Speed Memory Interfacing
Munich
12.07.2021
VERSAL ACAP Connectivity (3 days)
Berlin
12.07.2021
VERSAL ACAP Connectivity (5 days)
Berlin
26.07.2021
UltraScale FPGAs – Connectivity
Frankfurt
02.08.2021
Professional PCI Express
Frankfurt
01.09.2021
Designing with Multi-Gigabit Serial I/O
Frankfurt
06.09.2021
Designing with PCI Express
Munich
13.09.2021
ZYNQ – Board Design and High Speed Interfacing
Berlin
29.09.2021
Designing with Ethernet MAC Controllers
Berlin
04.10.2021
UltraScale FPGAs – Connectivity
Berlin
02.11.2021
High-Speed Memory Interfacing
Frankfurt
08.11.2021
Professional PCI Express
Freiburg
15.11.2021
Signal Integrity
Stuttgart
18.11.2021
Designing with Ethernet MAC Controllers
Frankfurt
18.11.2021
FPGA Board-Design
Stuttgart
22.11.2021
VERSAL ACAP Connectivity (3 days)
Stuttgart
22.11.2021
VERSAL ACAP Connectivity (5 days)
Stuttgart
06.12.2021
Designing with PCI Express
Berlin

Online Training

Date
Title
Location
29.01.2021
Xilinx Versal ACAP - From FPGA to Platform - WEBINAR
Online
02.02.2021
Vivado IP Flow - LIVE ONLINE
Online
03.02.2021
Acceleration Kernels with Versal AI Engine - WEBINAR
Online
08.02.2021
Git for EDA Tool Flows - LIVE ONLINE
Online
11.02.2021
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
16.02.2021
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Online
16.02.2021
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
16.02.2021
VHDL for Simulation - LIVE ONLINE
Online
16.02.2021
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
22.02.2021
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Online
22.02.2021
VHDL for Synthesis - LIVE ONLINE
Online
22.02.2021
Easy Start FPGA Vivado - LIVE ONLINE
Online
24.02.2021
Vivado Logic Analyzer - LIVE ONLINE
Online
25.02.2021
PCIe Protocol Overview - LIVE ONLINE
Online
01.03.2021
Vivado High-Level-Synthese for Hardware Designers - LIVE ONLINE
Online
02.03.2021
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Online
02.03.2021
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Online
04.03.2021
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
08.03.2021
Vivado Design Flow - LIVE ONLINE
Online
08.03.2021
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
09.03.2021
Introduction to Verification with OSVVM - LIVE ONLINE
Online
10.03.2021
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Online
11.03.2021
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
Online
23.03.2021
Advanced Verification with OSVVM - LIVE ONLINE
Online
Upon request
First-time Right Methods in ASIC and FPGA Design - WEBINAR
Online
Video on demand
Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE
Recorded
Video on demand
Running Multiple OS using XEN Hypervisior for Zynq US+ MPSoC - WEBINAR
Online
Video on demand
Dynamic Function eXchange (DFX) – reloading partial h/w function using Zynq MPSoC - WEBINAR
Online
Video on demand
New Features in VHDL 2019 - WEBINAR
Online

Seminars

No events for topic found

In-service training

PLC2 give further training for engineers and technicians.  Our structured trainingprogram provides the Know-how for the entire development process.

You can choose between two certified trainings:

  • FPGA-Designer
  • FPGA-Designer/Embedded

If you are interested, please contact us. We are pleased to give you further Information. 

Contact Person


Michael Schwarz
training & organization