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Our training courses - Knowledge imparted competently

Workshop & Seminar program 2022

Each of our training courses has a clear goal: To impart knowledge competently. We carry out this goal, on the one hand, with a wide range of offerings, and on the other hand, with very customized support during the training courses.

It’s time to convert your Spartan-6 into the Xilinx 7-Series cost optimized family!

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Our E-Team experts follow a learning guide, they always focus on the individual strengths and needs of the participants. They focus on technical content and refrain from marketing aspects. Very important for us is: The knowledge we provide is always up to date with the respective technology. We train you in various areas involving embedded systems (among others): Easy Start, FPGA, DSP, Languages, Connectivity, Embedded, Verification, Image Processing, Technology.

Our experts will be at your side in more than 80 highly customised and specifically designed training courses. Every year, we teach more than 1,100 engineers, technicians, managing directors, buyers, project managers, developers and administrative staff at various locations in Germany or in-house. Our customers include hundreds of companies – mainly from Germany, Switzerland and Eastern Europe. We offer participants from the automotive, electronics, aerospace, military, medical, communication or IoT sectors a wide range of training in Xilinx technologies and hardware description languages. Besides our Face-to-Face trainings PLC2 offers also online trainings and webinars.

The length of the training is based on the trained content: You or your staff can attend a free one-day seminar, a two- /three-day workshop, or a five-day power workshop. Customer-specific training can also run over a period of several months. The PLC2 long-term training is an additional chance to get further education.

Business

Date
Title
Location
Upon request
Kommunikation und Feedback
Upon request
Gesunde Führung und Mindful Leadership
Upon request
Technik trifft Recht

Easy Start

Date
Title
Location
11.07.2022
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Frankfurt
25.07.2022
Easy Start Embedded for ZYNQ-7000 SoC Systems
Munich
25.07.2022
Easy Start FPGA Vivado - LIVE ONLINE
Online
01.08.2022
Easy Start FPGA Vivado
Stuttgart
26.09.2022
Easy Start with the Kria KV260 Vision AI Starter Kit
Freiburg
04.10.2022
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Berlin
10.10.2022
Easy Start Embedded for ZYNQ-7000 SoC Systems
Stuttgart
10.11.2022
Easy Start with the Kria KV260 Vision AI Starter Kit
Stuttgart
21.11.2022
Easy Start FPGA Vivado
Frankfurt
01.12.2022
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Freiburg
Upon request
Easy Start Embedded PetaLinux

FPGA

Date
Title
Location
07.06.2022
Vivado Logic Analyzer - LIVE ONLINE
Online
07.06.2022
Git for EDA Tool Flows - LIVE ONLINE
Online
07.06.2022
Advanced Verification with OSVVM - LIVE ONLINE
Online
08.06.2022
Compact VHDL for Simulation
Frankfurt
09.06.2022
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
20.06.2022
Professional VHDL Testbenches and Verification with OSVVM
Freiburg
20.06.2022
FPGA Design Techniques Essentials - LIVE ONLINE
Online
20.06.2022
VIVADO Design Suite Tool Flow
Stuttgart
21.06.2022
VHDL for Simulation - LIVE ONLINE
Online
21.06.2022
FPGA Design Techniques - LIVE ONLINE
Online
21.06.2022
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Stuttgart
27.06.2022
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
27.06.2022
VHDL for Synthesis - LIVE ONLINE
Online
27.06.2022
Spartan-6 to 7-Series/UltraScale+ Migration - LIVE ONLINE
Online
27.06.2022
Compact UltraScale/UltraScale+
Freiburg
27.06.2022
Vivado Design Flow - LIVE ONLINE
Online
28.06.2022
Developing for Mission Critical FPGA & SoC
Berlin
29.06.2022
Debugging Techniques Using the VIVADO Logic Analyzer
Freiburg
11.07.2022
Introduction to Verification with OSVVM - LIVE ONLINE
Online
11.07.2022
Professional FPGA
Freiburg
11.07.2022
Dynamic Function eXchange DXX
Stuttgart
18.07.2022
Professional VIVADO
Freiburg
18.07.2022
Vivado IP Flow - LIVE ONLINE
Online
18.07.2022
Professional FPGA Circuit Design Technique
Freiburg
18.07.2022
Frankfurt
18.07.2022
Continuous Integration for EDA Tools - LIVE ONLINE
Online
21.07.2022
Spartan-6 to 7-Series/UltraScale+ Migration - LIVE ONLINE
Online
25.07.2022
Professional VHDL
Freiburg
25.07.2022
SystemVerilog – Advanced Verification for FPGA Design
Berlin
28.07.2022
UVM Made Easy for FPGA Designers
Berlin
01.08.2022
Git for EDA Tool Flows - LIVE ONLINE
Online
03.08.2022
Compact FPGA Circuit Design Technique
Stuttgart
08.08.2022
Vivado Logic Analyzer - LIVE ONLINE
Online
08.08.2022
Advanced Verification with OSVVM - LIVE ONLINE
Online
09.08.2022
Compact VHDL Testbenches and Verification with OSVVM
Berlin
10.08.2022
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
12.09.2022
Designing with the Spartan-7 Family
Berlin
12.09.2022
Compact Verilog
Frankfurt
12.09.2022
Compact VHDL for Synthesis
Stuttgart
13.09.2022
FPGA Designer - long term training
Freiburg
15.09.2022
Compact UltraScale/UltraScale+
Frankfurt
15.09.2022
Compact VHDL for Simulation
Stuttgart
19.09.2022
Professional VHDL Testbenches and Verification with OSVVM
Freiburg
19.09.2022
VIVADO Design Suite Tool Flow
Frankfurt
20.09.2022
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Frankfurt
28.09.2022
Debugging Techniques Using the VIVADO Logic Analyzer
Stuttgart
28.09.2022
Developing for Mission Critical FPGA & SoC
Freiburg
05.10.2022
Compact FPGA Circuit Design Technique
Berlin
05.10.2022
Compact VHDL Testbenches and Verification with OSVVM
Munich
10.10.2022
Professional VIVADO
Freiburg
10.10.2022
Berlin
17.10.2022
Dynamic Function eXchange DXX
Freiburg
17.10.2022
SystemVerilog – Advanced Verification for FPGA Design
Freiburg
20.10.2022
UVM Made Easy for FPGA Designers
Freiburg
24.10.2022
Professional FPGA
Munich
24.10.2022
Professional VHDL
Frankfurt
02.11.2022
Designing with the Spartan-7 Family
Stuttgart
07.11.2022
Professional FPGA Circuit Design Technique
Freiburg
07.11.2022
Professional VHDL Testbenches and Verification with OSVVM
Stuttgart
07.11.2022
VIVADO Design Suite Tool Flow
Berlin
08.11.2022
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Berlin
16.11.2022
Compact UltraScale/UltraScale+
Stuttgart
21.11.2022
Compact VHDL for Synthesis
Munich
24.11.2022
Compact VHDL for Simulation
Munich
05.12.2022
Debugging Techniques Using the VIVADO Logic Analyzer
Frankfurt
05.12.2022
Professional VHDL
Freiburg
12.12.2022
Professional VIVADO
Freiburg
12.12.2022
Developing for Mission Critical FPGA & SoC
Frankfurt
12.12.2022
Compact Verilog
Stuttgart
19.12.2022
Freiburg
Upon request
Upon request
FPGA Power Optimization
Upon request
Advanced Vivado-Tcl-Scripting
Upon request
Designing with the XILINX Analog Mixed Signal Solution
Video on demand
Partially Constrained Record Types in VHDL-2008 or: How to wire components effectively? - WEBINAR
Online

Embedded

Date
Title
Location
07.06.2022
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
07.06.2022
ZYNQ-7000 SoC System Architecture
Berlin
08.06.2022
Frankfurt
08.06.2022
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Berlin
13.06.2022
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
13.06.2022
Compact ZYNQ-7000 SoC for HW Designers
Freiburg
13.06.2022
ZYNQ UltraScale+ MPSoC System Architecture
Frankfurt
13.06.2022
Embedded Linux Driver Development
Berlin
20.06.2022
Professional Versal ACAP
Stuttgart
20.06.2022
Compact Python for Embedded
Freiburg
20.06.2022
Professional Python for Embedded
Freiburg
20.06.2022
Professional ZYNQ UltraScale+ MPSoC
Freiburg
20.06.2022
Stuttgart
27.06.2022
Compact ZYNQ-7000 SoC for SW Designers
Berlin
27.06.2022
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
29.06.2022
Embedded Design with PetaLinux Tools
Frankfurt
29.06.2022
AXI Interface Technology
Frankfurt
29.06.2022
Secure Boot Features and Secure Boot Overview for Xilinx Versal ACAP - WEBINAR
Online
11.07.2022
Professional ZYNQ-7000 SoC
Freiburg
11.07.2022
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
Online
13.07.2022
Developing Multimedia Solutions with the VCU and GStreamer
Frankfurt
13.07.2022
Online
18.07.2022
Munich
18.07.2022
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Online
18.07.2022
Versal Architecture Essentials - LIVE ONLINE
Online
18.07.2022
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Online
25.07.2022
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Online
25.07.2022
Versal AI Engine Essentials - LIVE ONLINE
Online
27.07.2022
Compact Versal ACAP for HW Designers
Munich
01.08.2022
Compact Vitis for Acceleration
Freiburg
01.08.2022
Versal ACAP System Architecture
Stuttgart
01.08.2022
Versal Power and Board Design - Essentials - LIVE ONLINE
Online
03.08.2022
Compact Versal ACAP for SW Designers
Freiburg
08.08.2022
Freiburg
09.08.2022
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Berlin
15.08.2022
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
23.08.2022
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Berlin
05.09.2022
Compact Python for Embedded
Frankfurt
05.09.2022
Professional Python for Embedded
Frankfurt
05.09.2022
Freiburg
08.09.2022
ZYNQ-7000 SoC System Architecture
Freiburg
12.09.2022
Professional Versal ACAP
Frankfurt
12.09.2022
Compact ZYNQ-7000 SoC for SW Designers
Freiburg
12.09.2022
AXI Interface Technology
Berlin
12.09.2022
PCI Express Hands-on System Development
Frankfurt
14.09.2022
Embedded Design with PetaLinux Tools
Berlin
15.09.2022
ZYNQ UltraScale+ MPSoC System Architecture
Freiburg
19.09.2022
Compact ZYNQ-7000 SoC for HW Designers
Frankfurt
19.09.2022
Professional ZYNQ UltraScale+ MPSoC
Freiburg
19.09.2022
Compact Embedded Linux
Munich
19.09.2022
Designing with RF Data Converters
Stuttgart
20.09.2022
Compact Vitis for Software Designers
Berlin
26.09.2022
Stuttgart
28.09.2022
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Frankfurt
05.10.2022
Compact Versal ACAP for SW Designers
Berlin
05.10.2022
FPGA Designer Embedded - long term training
Freiburg
06.10.2022
Developing Multimedia Solutions with the VCU and GStreamer
Berlin
12.10.2022
Compact Versal ACAP for HW Designers
Stuttgart
17.10.2022
Frankfurt
24.10.2022
Professional ZYNQ-7000 SoC
Freiburg
02.11.2022
Compact ZYNQ-7000 SoC for SW Designers
Frankfurt
07.11.2022
Professional Versal ACAP
Freiburg
07.11.2022
Berlin
14.11.2022
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Freiburg
14.11.2022
Compact Vitis for Acceleration
Frankfurt
21.11.2022
ZYNQ-7000 SoC System Architecture
Munich
21.11.2022
Professional Python for Embedded
Berlin
21.11.2022
Embedded Linux Driver Development
Freiburg
21.11.2022
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Munich
21.11.2022
Compact Python for Embedded
Berlin
23.11.2022
Versal ACAP System Architecture
Munich
28.11.2022
Berlin
29.11.2022
Embedded Design with PetaLinux Tools
Munich
29.11.2022
AXI Interface Technology
Munich
01.12.2022
ZYNQ UltraScale+ MPSoC System Architecture
Munich
05.12.2022
Compact Vitis for Software Designers
Munich
05.12.2022
PCI Express Hands-on System Development
Stuttgart
12.12.2022
Designing with RF Data Converters
Munich
12.12.2022
Compact ZYNQ-7000 SoC for HW Designers
Munich
12.12.2022
Professional ZYNQ UltraScale+ MPSoC
Frankfurt
19.12.2022
Munich
19.12.2022
Advanced ZYNQ Ultrascale+ MPSoC for HW Designers
Stuttgart
Upon request
High-Speed Ethernet – Hands-On System Development
Upon request
Professional MicroBlaze System Design
Upon request
RISC-V Core Verification and Compliance Testing
Upon request
Migrate to Real-Time OS: Hands-On System Development
Upon request
Real-Time Control System Development using RTOS
Upon request
Essentials of Microprocessors
Upon request
RISC-V Architecture and FPGA Implementation
Video on demand
Xilinx Versal ACAP - Creating a Custom Embedded Platform - WEBINAR
Online
Video on demand
Introduction into ROS Video Application Acceleration using Kria SOM and Vitis Tools - WEBINAR
Online
Video on demand
Designing with IP Integrator Tool 101 - WEBINAR
Online
Video on demand
Xilinx Versal ACAP – Application acceleration on heterogenous platforms - WEBINAR
Online
Video on demand
Acceleration Kernels with Versal AI Engine - WEBINAR
Online
Video on demand
Embedded Device Driver Management in Vitis - WEBINAR
Online
Video on demand
Vitis Tools for Acceleration - Creating a RTL Kernel: from HDL to reusable packaged Kernel - WEBINAR
Online
Video on demand
Introduction to AI Applications using Kria SoM - WEBINAR
Online
Video on demand
Vitis AI - Creating an Edge Inference Solution - WEBINAR
Online

DSP & Image Processing

Date
Title
Location
05.09.2022
DSP Design using System Generator
Freiburg
05.09.2022
Expert DSP Design
Freiburg
08.09.2022
Model Composer
Freiburg
05.12.2022
DSP Design using System Generator
Berlin
05.12.2022
Expert DSP Design
Berlin
08.12.2022
Model Composer
Berlin

Connectivity

Date
Title
Location
13.06.2022
High-Speed Memory Interfacing
Munich
20.06.2022
Signal Integrity
Berlin
23.06.2022
FPGA Board-Design
Berlin
11.07.2022
VERSAL ACAP Connectivity (5 days)
Berlin
11.07.2022
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Online
18.07.2022
PCIe Protocol Overview - LIVE ONLINE
Online
18.07.2022
DDR4 Interfacing with XILINX FPGAs
Frankfurt
25.07.2022
UltraScale FPGAs – Connectivity
Frankfurt
25.07.2022
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Online
01.08.2022
Professional PCI Express
Frankfurt
05.09.2022
Designing with Multi-Gigabit Serial I/O
Frankfurt
12.09.2022
Designing with PCI Express
Munich
14.09.2022
Designing with Ethernet MAC Controllers
Berlin
26.09.2022
ZYNQ – Board Design and High Speed Interfacing
Berlin
24.10.2022
UltraScale FPGAs – Connectivity
Berlin
02.11.2022
High-Speed Memory Interfacing
Frankfurt
07.11.2022
VERSAL ACAP Connectivity (5 days)
Stuttgart
14.11.2022
Professional PCI Express
Freiburg
17.11.2022
Designing with Ethernet MAC Controllers
Freiburg
21.11.2022
Signal Integrity
Stuttgart
24.11.2022
FPGA Board-Design
Stuttgart
05.12.2022
Designing with PCI Express
Berlin
19.12.2022
DDR4 Interfacing with XILINX FPGAs
Stuttgart

Online Training

Date
Title
Location
07.06.2022
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
07.06.2022
Vivado Logic Analyzer - LIVE ONLINE
Online
07.06.2022
Git for EDA Tool Flows - LIVE ONLINE
Online
07.06.2022
Advanced Verification with OSVVM - LIVE ONLINE
Online
09.06.2022
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
13.06.2022
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
20.06.2022
FPGA Design Techniques Essentials - LIVE ONLINE
Online
21.06.2022
VHDL for Simulation - LIVE ONLINE
Online
21.06.2022
FPGA Design Techniques - LIVE ONLINE
Online
27.06.2022
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
27.06.2022
VHDL for Synthesis - LIVE ONLINE
Online
27.06.2022
Spartan-6 to 7-Series/UltraScale+ Migration - LIVE ONLINE
Online
27.06.2022
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
27.06.2022
Vivado Design Flow - LIVE ONLINE
Online
29.06.2022
Secure Boot Features and Secure Boot Overview for Xilinx Versal ACAP - WEBINAR
Online
11.07.2022
Introduction to Verification with OSVVM - LIVE ONLINE
Online
11.07.2022
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Online
11.07.2022
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
Online
13.07.2022
Online
18.07.2022
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Online
18.07.2022
PCIe Protocol Overview - LIVE ONLINE
Online
18.07.2022
Vivado IP Flow - LIVE ONLINE
Online
18.07.2022
Versal Architecture Essentials - LIVE ONLINE
Online
18.07.2022
Continuous Integration for EDA Tools - LIVE ONLINE
Online
18.07.2022
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Online
21.07.2022
Spartan-6 to 7-Series/UltraScale+ Migration - LIVE ONLINE
Online
25.07.2022
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Online
25.07.2022
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Online
25.07.2022
Easy Start FPGA Vivado - LIVE ONLINE
Online
25.07.2022
Versal AI Engine Essentials - LIVE ONLINE
Online
01.08.2022
Git for EDA Tool Flows - LIVE ONLINE
Online
01.08.2022
Versal Power and Board Design - Essentials - LIVE ONLINE
Online
08.08.2022
Vivado Logic Analyzer - LIVE ONLINE
Online
08.08.2022
Advanced Verification with OSVVM - LIVE ONLINE
Online
10.08.2022
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
15.08.2022
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
13.09.2022
FPGA Designer - long term training
Freiburg
Video on demand
Xilinx Versal ACAP - Creating a Custom Embedded Platform - WEBINAR
Online
Video on demand
Introduction into ROS Video Application Acceleration using Kria SOM and Vitis Tools - WEBINAR
Online
Video on demand
Designing with IP Integrator Tool 101 - WEBINAR
Online
Video on demand
Xilinx Versal ACAP – Application acceleration on heterogenous platforms - WEBINAR
Online
Video on demand
Partially Constrained Record Types in VHDL-2008 or: How to wire components effectively? - WEBINAR
Online
Video on demand
Acceleration Kernels with Versal AI Engine - WEBINAR
Online
Video on demand
Embedded Device Driver Management in Vitis - WEBINAR
Online
Video on demand
Vitis Tools for Acceleration - Creating a RTL Kernel: from HDL to reusable packaged Kernel - WEBINAR
Online
Video on demand
Introduction to AI Applications using Kria SoM - WEBINAR
Online

Seminars

Date
Title
Location
20.09.2022
FPGA Schaltungstechnik - PLC2
Freiburg
18.10.2022
Schaltungssynthese mit VHDL - PLC2
Stuttgart
15.11.2022
Schaltungssimulation mit VHDL - PLC2
Frankfurt

In-service training

PLC2 give further training for engineers and technicians.  Our structured trainingprogram provides the Know-how for the entire development process.

You can choose between two certified trainings:

  • FPGA-Designer
  • FPGA-Designer/Embedded

If you are interested, please contact us. We are pleased to give you further Information. 

Contact Person


Michael Schwarz
training & organization