Our training courses - Knowledge imparted competently

Each of our training courses has a clear goal: To impart knowledge competently. We carry out this goal, on the one hand, with a wide range of offerings, and on the other hand, with very customized support during the training courses.

Our E-Team experts follow a learning guide, they always focus on the individual strengths and needs of the participants. They focus on technical content and refrain from marketing aspects. Very important for us is: The knowledge we provide is always up to date with the respective technology. We train you in various areas involving embedded systems (among others): Easy Start, FPGA, DSP, Languages, Connectivity, Embedded, Verification, Image Processing, Technology.

Our experts will be at your side in more than 80 highly customised and specifically designed training courses. Every year, we teach more than 1,100 engineers, technicians, managing directors, buyers, project managers, developers and administrative staff at various locations in Germany or in-house. Our customers include hundreds of companies – mainly from Germany, Switzerland and Eastern Europe. We offer participants from the automotive, electronics, aerospace, military, medical, communication or IoT sectors a wide range of training in Xilinx technologies and hardware description languages. Besides our Face-to-Face trainings PLC2 offers also online trainings. Webinars, Shorties and PLC2 online trainings.

The length of the training is based on the trained content: You or your staff can attend a free one-day seminar, a two- /three-day workshop, or a five-day power workshop. Customer-specific training can also run over a period of several months. The PLC2 long-term training is an additional chance to get further education.

Easy Start

Date
Title
Location
09.11.2020
Easy Start FPGA Vivado
Frankfurt
08.12.2020
Easy Start FPGA Vivado - LIVE ONLINE
Online
16.12.2020
Easy Start Embedded for ZYNQ UltraScale+ MPSoC Systems
Freiburg
Upon request
Easy Start Embedded PetaLinux

FPGA

Date
Title
Location
02.11.2020
Compact UltraScale/UltraScale+
Stuttgart
09.11.2020
Professional VHDL Testbenches and Verification with OSVVM
Stuttgart
09.11.2020
VIVADO Design Suite Tool Flow
Berlin
10.11.2020
VIVADO Design Suite Static Timing Analysis and XILINX Design Constraints
Berlin
10.11.2020
Advanced Verification with OSVVM - LIVE ONLINE
Online
11.11.2020
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
16.11.2020
Compact VHDL for Synthesis
Munich
16.11.2020
Professional FPGA Design Techniques
Freiburg
18.11.2020
Vivado Design Flow - LIVE ONLINE
Online
19.11.2020
Designing with the Spartan-7 Family
Stuttgart
19.11.2020
Compact VHDL for Simulation
Munich
23.11.2020
Git for EDA Tool Flows - LIVE ONLINE
Online
25.11.2020
Compact Verilog
Stuttgart
27.11.2020
New Features in VHDL 2019 - WEBINAR
Online
30.11.2020
Vivado IP Flow - LIVE ONLINE
Online
01.12.2020
Debugging Techniques Using the VIVADO Logic Analyzer
Frankfurt
01.12.2020
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
01.12.2020
VHDL for Simulation - LIVE ONLINE
Online
01.12.2020
Freiburg
07.12.2020
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Online
07.12.2020
Professional VHDL
Freiburg
07.12.2020
Developing for Mission Critical FPGA & SoC
Frankfurt
10.12.2020
Vivado Logic Analyzer - LIVE ONLINE
Online
14.12.2020
Professional VIVADO
Freiburg
15.12.2020
VHDL for Synthesis - LIVE ONLINE
Online
15.12.2020
Introduction to Verification with OSVVM - LIVE ONLINE
Online
25.01.2021
Compact FPGA Design Techniques
Freiburg
15.02.2021
Continuous Integration
Stuttgart
Upon request
FPGA Designer - long term training
Freiburg
Upon request
Upon request
FPGA Power Optimization
Upon request
Expert FPGA Design Techniques
Upon request
Upon request
Advanced Vivado-Tcl-Scripting
Upon request
Designing with the XILINX Analog Mixed Signal Solution
Upon request
First-time Right Methods in ASIC and FPGA Design - WEBINAR
Online
Video on demand
Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE
Recorded

Embedded

Date
Title
Location
02.11.2020
Professional Python for Embedded
Berlin
02.11.2020
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
02.11.2020
Compact ZYNQ-7000 SoC for SW Designers
Frankfurt
02.11.2020
Compact Python for Embedded
Berlin
05.11.2020
ZYNQ-7000 SoC System Architecture
Munich
09.11.2020
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Online
09.11.2020
Compact ZYNQ UltraScale+ MPSoC for SW Designers
Freiburg
12.11.2020
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
Online
16.11.2020
PCIe Protocol Overview - LIVE ONLINE
Online
16.11.2020
Compact ZYNQ UltraScale+ MPSoC for HW Designers
Munich
17.11.2020
Compact Vitis for Acceleration
Frankfurt
01.12.2020
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
01.12.2020
AXI Interface Technology
Munich
01.12.2020
PCI Express Hands-on System Development
Stuttgart
03.12.2020
Embedded Design with PetaLinux Tools
Munich
07.12.2020
Professional Vitis
Berlin
07.12.2020
Compact ZYNQ-7000 SoC for HW Designers
Munich
08.12.2020
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
08.12.2020
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Online
10.12.2020
XILINX SDSoC
Berlin
10.12.2020
ZYNQ UltraScale+ MPSoC System Architecture
Munich
14.12.2020
Professional SDSoC
Frankfurt
14.12.2020
Professional ZYNQ UltraScale+ MPSoC
Frankfurt
15.12.2020
Compact Vitis AI
Berlin
21.12.2020
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Online
25.01.2021
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
25.01.2021
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Online
Upon request
Debug your Linux – Praktisches Debuggen auf echter Hardware
Upon request
Upon request
Professional ML / AI
Upon request
Upon request
High-Speed Ethernet – Hands-On System Development
Upon request
Designing with RF Data Converters
Upon request
Professional MicroBlaze System Design
Upon request
Embedded Linux Development with Yocto Project
Upon request
Embedded Linux Driver Development
Upon request
Real-Time Control System Development using RTOS
Upon request
Essentials of Microprocessors

DSP & Image Processing

Date
Title
Location
23.11.2020
Vivado High-Level-Synthese for Hardware Designers - LIVE ONLINE
Online
23.11.2020
Munich
01.12.2020
Advanced VIVADO HLS
Munich
07.12.2020
DSP Design using System Generator
Berlin
07.12.2020
Expert DSP Design using System Generator
Berlin
10.12.2020
Accelerating OpenCV Functions with Vivado HLS
Frankfurt
10.12.2020
Model Composer
Berlin

Connectivity

Date
Title
Location
02.11.2020
VERSAL ACAP Connectivity (3 days)
Stuttgart
02.11.2020
VERSAL ACAP Connectivity (5 days)
Stuttgart
05.11.2020
Designing with Ethernet MAC Controllers
Frankfurt
09.11.2020
Professional PCI Express
Freiburg
16.11.2020
Signal Integrity
Stuttgart
19.11.2020
FPGA Board-Design
Stuttgart
24.11.2020
High-Speed Memory Interfacing
Frankfurt
01.12.2020
DDR4 Interfacing with XILINX FPGAs
Stuttgart
14.12.2020
Designing with PCI Express
Berlin

Online Training

Date
Title
Location
02.11.2020
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
09.11.2020
Designing an Integrated PCI Express System PCIe Gen3 - LIVE ONLINE
Online
10.11.2020
Advanced Verification with OSVVM - LIVE ONLINE
Online
11.11.2020
UltraScale/UltraScale+ Architecture - LIVE ONLINE
Online
12.11.2020
Migrating to the Vitis Embedded Software Development - LIVE ONLINE
Online
16.11.2020
PCIe Protocol Overview - LIVE ONLINE
Online
18.11.2020
Vivado Design Flow - LIVE ONLINE
Online
23.11.2020
Git for EDA Tool Flows - LIVE ONLINE
Online
23.11.2020
Vivado High-Level-Synthese for Hardware Designers - LIVE ONLINE
Online
27.11.2020
New Features in VHDL 2019 - WEBINAR
Online
30.11.2020
Vivado IP Flow - LIVE ONLINE
Online
01.12.2020
Vivado Timing Constraints and Analysis - LIVE ONLINE
Online
01.12.2020
VHDL for Simulation - LIVE ONLINE
Online
01.12.2020
Zynq UltraScale+ MPSoC for the System Architect - LIVE ONLINE
Online
07.12.2020
Designing with Xilinx Serial Transceivers - LIVE ONLINE
Online
08.12.2020
Zynq 7000 SoC for the Hardware Designer - LIVE ONLINE
Online
08.12.2020
Easy Start FPGA Vivado - LIVE ONLINE
Online
08.12.2020
Zynq 7000 SoC for the Software Designer - LIVE ONLINE
Online
10.12.2020
Vivado Logic Analyzer - LIVE ONLINE
Online
15.12.2020
VHDL for Synthesis - LIVE ONLINE
Online
15.12.2020
Introduction to Verification with OSVVM - LIVE ONLINE
Online
21.12.2020
Zynq UltraScale+ MPSoC for the Software Designer - LIVE ONLINE
Online
25.01.2021
Zynq UltraScale+ MPSoC for the Hardware Designer - LIVE ONLINE
Online
25.01.2021
Designing with the Zynq UltraScale+ RFSoC - LIVE ONLINE
Online
Upon request
First-time Right Methods in ASIC and FPGA Design - WEBINAR
Online
Video on demand
Design, Constraining and Verification of Low Speed and High Speed ADC Interfaces - SHORTIE
Recorded

Seminars

No events for topic found

In-service training

PLC2 give further training for engineers and technicians.  Our structured trainingprogram provides the Know-how for the entire development process.

You can choose between two certified trainings:

  • FPGA-Designer
  • FPGA-Designer/Embedded

If you are interested, please contact us. We are pleased to give you further Information. 

Contact Person


Michael Schwarz
training & organization