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Versal AI Engine Essentials - LIVE ONLINE - February 15, 2021

With the Versal Adaptive Compute Acceleration Platform (ACAP) Xilinx introduces devices with a special AI Engine unit. The AI Engine offers high performance, low latency capabilities for advanced data processing.

This course headstarts algorithm programmers to deploy C/C++ kernels on Versal AI Engine. Starting off the basic elements of the Versal AI Engine, it’s processing units and interfaces, the connections of datapath and the memory hierarchy in the regular grid of the AIE tiles are presented. The AI Engine is set up with the Vitis toolchain to run acceleration functions written in C/C++ code. The handling of the tools including debugging capabilities and analysis features are introduced along according examples and labs.

   10% OFF on all Versal trainings until March 31, 2021

   Versal AI Engine Essentials

Versal Architecture Essentials - LIVE ONLINE - February 17, 2021

With Versal, Xilinx offers the first highly integrated chip series in the new ACAP family - Adaptive Compute Acceleration Platform.

The Versal Chips have a heterogeneous architecture with MPSoC, FPGA, PCIe Connectivity, Memory Management, DSP Engines and AI Engines, which in particular enable software and DSP applications to be parallelized and partitioned in hardware to enable the optimal hardware units usage for the specific task.

In this workshop you will be familiarized with the architecture in order to be able to use the building blocks optimally for demanding tasks. The technical features and optimal use of the components are described in order to compile software and hardware functions on specific hardware units.

   10% OFF on all Versal trainings until March 31, 2021

   Versal Architecture Essentials

Vitis Acceleration Methodology - LIVE ONLINE - February 23, 2021

The Vitis™ unified software platform tool combines all aspects of Xilinx® software development and for acceleration purpose this includes the embedded software development flow for the processors and the hardware development flow for specific function calls selected for offloading to hardware.

In this online session you will learn the methodology and development processes in the context of Linux based embedded processing on Xilinx Zynq technology.

The acceleration modules need to be defined as kernel modules and can be developed using C/C++, OpenCL C, or RTL. Software/hardware engineers and application developers can benefit from the Vitis™ unified software environment when using the OpenCL framework with support for the acceleration flow.

   Vitis Acceleration Methodology

Vitis AI – Getting Started - LIVE ONLINE - March 15, 2021

This course introduces the Vitis AI development Toolkit for the AI inference on Xilinx Hardware platforms in conjunction with DNN algorithms, model inference, associated frameworks for model development.

The basics of Machine Learning (ML) and challenges in Neural Network scenarios are revisited. Along with input of pre-trained models either from Tensorflow or Caffe the cncepts of the Vitis AI development kit are shown with tools to prune and optimize the trained models. This provides a properly scaled base for mapping. From this the AI Compiler generates deployable code that can then be run on a FPGA fabric microarchitecture. To efficiently ramp and properly evaluate such a project, Vitis AI development kit tools can be used for analyzing the model performance and debugging.

   Vitis AI – Getting Started