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L5

New on the market: L5 (De-) Compression IP for FPGAs

The PLC2 Lightweight, Low Latency, Low Power & Lossless (L5) Compression IP is an image compression IP for FPGAs. It is packaged with Xilinx AXI-streaming interfaces to be seamlessly attached to existing image processing applications. With the PLC2 L5 compression you can achieve state of the art sub-frame latency combined with low power consumption and a lightweight implementation in terms of resource consumption and lossless decompression for a wide range of applications on the edge and in the cloud, without having to invest in new and powerful hardware. The target use cases for our L5 (De-) Compression IP are camera based applications in the automotive industry (including heavy duty trucks), railway applications, robots, drones, etc. With data reduction up to 60% you will be able to create room for future usage of higher resolution sensors and new types of applications.

 

 

I am very excited with our brand-new compression IP which will deliver significant value to our broad customer range worldwide due to the fact we can deliver maximum compression with a very small footprint in size and power cost.“

Stefan Krassin, CEO PLC2 Design GmbH

L5 Compression IP in detail

Most applications have a strong requirement for not loosing a single bit within an image to ensure a correct behavior of the attached system like e.g. reaction on objects and the reaction time, loosing a frame which is a key frame in a multi-frame compression like e.g. H.265 is leading to missed scenes or wrong measures. We at PLC2 see a camera as a sensor and the image as a measure. All changes to the measure are also changing the reaction which are then based on a wrong assumption. L5 Compression is true Lossless to prevent from issues in that manner.

All kinds of applications like e.g. ADAS systems, control tasks in robotics and live transmissions where some reactions are being taken, require a low latency to reflect the scene at the reaction side (algorithm, operator, etc.) as fast as possible. A scenario where e.g. a kid is visualized at the screen to appear while driving backwards with a car after a crash happens is not desired and can only be prevented if the system using image compression has a low latency. We at PLC2 believe in that and have designed our L5 core to have a latency of below one frame time for the whole transmission chain (encoding and decoding together). We can achieve that in addition without the need for external memory.

Integrating a module into an existing image processing chain or a transmission chain is a challenge by nature. If using an FPGA in addition the integration into an existing design where the placement has already been done could be hard if the addition consumes a lot of resources. We designed the L5 Compression IP to have standard interfaces like e.g. AXI4-Stream and to be compatible with the AXI4-Stream Video Protocol of Xilinx. In addition the resource usage is quite small to fit even into smallest FPGAs and is easy adaptable for different architectures as it also does not require the usage of external resources like e.g. DDR memory.

Current trends are to reduce the power footprint of the applications to get most applications battery powered. Using the L5 Compression IP with its small resource usage makes it optimal for all applications needing a image compression without spending an additional power consuming chip or requiring power expensive external memory accesses.

 

Willard Tu, senior director of automotive at Xilinx, said:


“We’re extremely pleased to be working with PLC2, providing Xilinx AXI-streaming interfaces that can be easily attached to image processing applications. Using Xilinx technology, PLC2 can now offer automotive customers sophisticated functionality and even greater value, enabling them to save up to 60% of storage by compressing videos captured during ADAS data logging.”

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