Architecture and Technology
- CoolRunner CPLDs
- Basic Virtex-II Architecture
- Advanced Virtex-II Architecture
- Basic Virtex-II PRO Architecture
- Advanced Virtex-II PRO Architecture
- Basic Virtex-4 Architecture
- Basic Virtex-5 Architecture
- Advanced Virtex-4 Architecture
- Advanced Virtex-5 Architecture
- Virtex-4/5/6 DSP-Blocks
- Virtex-4/5/6 BRAM and FIFOs
- EMAC Controllers
- Virtex-4/5/6 Interfacing
- Virtex-5/6 und Spartan-6 PCIe
- Spartan-6 BRAM and Memory Controller Block
- Basic Virtex/Spartan-6 Architecture
- Spartan-6 Interfacing
- Spartan-6 BRAM and Memory Controller Block-High Speed
IO
- Configuration Debugging
- Bitstream Encryption
- Generating Configuration Files
- Board Design
- Signal Integrity
Basic Design Entry and Design Flow
- XILINX Tool Flow
- Projects in the Project Navigator
- ECS - Engineering Capture Station
- Core Generator System
XILINX HDL Design Flow
- VHDL/Verilog Synthesis in the Project Navigator
- Synthesis Techniques
- XST Synthesis
- XST Constraints
- Direct Instantiation of XILINX Components
- State Machine Implementation
- XILINX specific Attributes
- IP Cores and the XILINX CORE Generator
- Synthesis of IP Based Systems
VHDL Design Entry
- Introduction to VHDL
- Review of basic VHDL
- VHDL Design Guide Lines
- VHDL Language Concepts
- VHDL Type Concept
- VHDL Operators
- VHDL Concurrent and Sequential Statements
- VHDL Controlled Operations Statements
- VHDL Subprograms/ Functions and Procedures
- VHDL Build-in Packages
- VHDL Structural Modeling
- VHDL Processes
- VHDL Finite State Maschines
- VHDL Define your own Packages
- VHDL Generics and Attributes
- VHDL Designing re-usable Components
- VHDL Coding Style for XILINX FPGAs
- Loops
Verilog Design Entry
- Introduction to Verilog
- Verilog Design Guide Lines
- Verilog Structural and Hardware Modeling
- Verilog Language Concepts
- Verilog Coding Style
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VHDL/Verilog based Verification
- Simulation and Testbenches
- The Verilog Test Fixture Concept
- The VHDL Test Bench Concept
- The VHDL Build-In Timing Model
- VHDL Attributes
- HDL Bencher
- Modeling external Components
- Introduction to Testbenches
- Advanced Testbenches
- VHDL Build-In Packages for File I/O
- VHDL Configuration and IP Cores
- Verification of IP based Systems
- Assertion Based Verification
DSP Design Entry and Design Flow
- XILINX Tool Flow using XILINX System Generator
- XILINX System Generator
- Simulink Projects
- XILINX Tool Flow using Synplify DSP Flow
- Synplify DSP
HDL Synthesis
- Introduction to Synthesis
- XILINX XST
FPGA Implementation
- Basic Implementation Options
- Advanced Control through Scripting
- Command Line Implementation
- UCF Editing
- Reduce Debug Time
- FPGA Design Techniques I
- FPGA Design Techniques II
FPGA Optimization
- Timing Constraints I
- Timing Constraints II
- Timing Constraints III
- Multiple Place & Route
- Creating your own RPM
- Handcrafting Performance
- Incremental Design Techniques
- PlanAhead Overview
- PlanAhead: IO Pin and Clock Planning
- PlanAhead: RTL Development and Analysis
- PlanAhead: Implementing a Design
- PlanAhead: Design Analysis
- PlanAhead: Floorplanning Techniques
- PlanAhead: Debugging with ChipScope
FPGA Verification
- Reading Reports
- Introduction to Timing Analyzer
- FPGA Editor
- ChipScope PRO
Applications
- Designing a PCI System with
XILINX FPGAs
- Designing a PCI Express System
- DSP Implementation Techniques
- Designing fast Memory Controller
Processors
- MicroBlaze- Embedded Design for
XILINX FPGAs
- System Design with PowerPC /
Virtex-II PRO
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